RT5350 reg 0x48:2=1 CPU PLL is 240Mhz, =0 CPU PLL is CFG0_CPUCLK
 liushiwei@gmail.com  


diff -uNra linux-3.10.36/arch/mips/include/asm/mach-ralink/rt305x.h linux-3.10.36.orig/arch/mips/include/asm/mach-ralink/rt305x.h
--- linux-3.10.36/arch/mips/include/asm/mach-ralink/rt305x.h	2014-05-15 00:25:12.209756390 +0800
+++ linux-3.10.36.orig/arch/mips/include/asm/mach-ralink/rt305x.h	2014-05-11 17:02:08.000000000 +0800
@@ -91,6 +91,11 @@
 #define RT3352_SYSCFG0_CPUCLK_LOW	0x0
 #define RT3352_SYSCFG0_CPUCLK_HIGH	0x1
 
+#define RT5350_CPU_PLL_DYN	0x48
+#define RT5350_CPU_PLL_DYN_MASK  2
+#define RT5350_CPU_PLL_DYN_240   2
+#define RT5350_CPU_PLL_DYN_360   0
+
 #define RT5350_SYSCFG0_CPUCLK_SHIFT	8
 #define RT5350_SYSCFG0_CPUCLK_MASK	0x3
 #define RT5350_SYSCFG0_CPUCLK_360	0x0
diff -uNra linux-3.10.36/arch/mips/ralink/rt305x.c linux-3.10.36.orig/arch/mips/ralink/rt305x.c
--- linux-3.10.36/arch/mips/ralink/rt305x.c	2014-05-15 00:25:46.849757544 +0800
+++ linux-3.10.36.orig/arch/mips/ralink/rt305x.c	2014-05-11 16:49:34.000000000 +0800
@@ -207,6 +180,8 @@
 		default:
 			BUG();
 		}
+		if((rt_sysc_r32(RT5350_CPU_PLL_DYN) & RT5350_CPU_PLL_DYN_MASK) == RT5350_CPU_PLL_DYN_240) 
+			cpu_rate=240000000;
 		uart_rate = 40000000;
 		wdt_rate = sys_rate;
 	} else {